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121 In Stock

74LVC2G74DP-Q100

121 In Stock

74LVC2G74DP-Q100

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Manufacturer No:

Nexperia

Manufacturer:

Nexperia

Category:

FF/Latches

Package:

TSSOP

Datasheet:

Description Differential:

D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO8

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    Type

    DESCRIPTION

    Width

    3 mm

    Family

    LVC/LCX/Z

    Length

    3 mm

    HTS Code

    8542.39.00.01

    fmax-Min

    200 MHz

    Max I(ol)

    0.032 A

    Rohs Code

    Yes

    Popularity

    42

    Technology

    CMOS

    JESD-30 Code

    S-PDSO-G8

    Package Code

    TSSOP

    Trigger Type

    POSITIVE EDGE

    JESD-609 Code

    e4

    Logic IC Type

    D FLIP-FLOP

    Package Shape

    SQUARE

    Package Style

    SMALL OUTLINE, THIN PROFILE, SHRINK PITCH

    Surface Mount

    YES

    Terminal Form

    GULL WING

    Number of Bits

    1

    Terminal Pitch

    0.65 mm

    Output Polarity

    COMPLEMENTARY

    Screening Level

    AEC-Q100

    Terminal Finish

    NICKEL PALLADIUM GOLD SILVER

    Seated Height-Max

    1.1 mm

    Temperature Grade

    AUTOMOTIVE

    Terminal Position

    DUAL

    Source Content uid

    74LVC2G74DP-Q100

    Number of Functions

    1

    Number of Terminals

    8

    Package Description

    TSSOP,

    Part Life Cycle Code

    Active

    Load Capacitance (CL)

    50 pF

    Package Body Material

    PLASTIC/EPOXY

    Reach Compliance Code

    compliant

    Propagation Delay (tpd)

    13.4 ns

    Package Equivalence Code

    TSSOP8,.16

    Operating Temperature-Max

    125°C

    Operating Temperature-Min

    -40°C

    Supply Voltage-Max (Vsup)

    5.5 V

    Supply Voltage-Min (Vsup)

    1.65 V

    Supply Voltage-Nom (Vsup)

    1.8 V

    Moisture Sensitivity Level

    1

    Peak Reflow Temperature (Cel)

    260

    Power Supply Current-Max (ICC)

    0.004 mA

    Time@Peak Reflow Temperature-Max (s)

    30

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