Width

3.95 mm

YTEOL

3.5

Family

LV/LV-A/LVX/H

Length

8.65 mm

HTS Code

8542.39.00.01

Objectid

1867571306

Max I(ol)

6 A

Pin Count

14

Risk Rank

7.1

Rohs Code

No

Technology

CMOS

Pbfree Code

No

Subcategory

Gates

JESD-30 Code

R-PDSO-G14

Package Code

SOP

Logic IC Type

NAND GATE

Package Shape

RECTANGULAR

Package Style

SMALL OUTLINE

Surface Mount

YES

Terminal Form

GULL WING

Packing Method

TR

Power Supplies

3.3 V

Terminal Pitch

1.27 mm

Schmitt Trigger

NO

Number of Inputs

2

Part Package Code

SOIC

Seated Height-Max

1.75 mm

Temperature Grade

INDUSTRIAL

Terminal Position

DUAL

Source Content uid

HD74LV00ARPEL

Number of Functions

4

Number of Terminals

14

Package Description

SOP, SOP14,.25

Prop. Delay@Nom-Sup

13 ns

Part Life Cycle Code

Active

Qualification Status

Not Qualified

Load Capacitance (CL)

50 pF

Package Body Material

PLASTIC/EPOXY

Reach Compliance Code

compliant

Propagation Delay (tpd)

20 ns

Package Equivalence Code

SOP14,.25

Operating Temperature-Max

85°C

Operating Temperature-Min

-40°C

Supply Voltage-Max (Vsup)

5.5 V

Supply Voltage-Min (Vsup)

2 V

Supply Voltage-Nom (Vsup)

2.5 V

Moisture Sensitivity Level

1