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IDT74LVC112ADC
1565 In Stock
IDT74LVC112ADC
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Manufacturer No:
Integrated Device Technology Inc
Manufacturer:
Integrated Device Technology Inc
Category:
FF/Latches
Package:
Datasheet:
Description Differential:
J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, SOIC-16
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Type
DESCRIPTION
Width
3.9 mm
Family
LVC/LCX/Z
Length
9.9 mm
HTS Code
8542.39.00.01
Objectid
1484339795
fmax-Min
150 MHz
Max I(ol)
0.024 A
Pin Count
16
Risk Rank
9.01
Rohs Code
No
Technology
CMOS
Subcategory
FF/Latches
JESD-30 Code
R-PDSO-G16
Package Code
SOP
Trigger Type
NEGATIVE EDGE
JESD-609 Code
e0
Logic IC Type
J-K FLIP-FLOP
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE
Surface Mount
YES
Terminal Form
GULL WING
Number of Bits
2
Power Supplies
3.3 V
Terminal Pitch
1.27 mm
Output Polarity
COMPLEMENTARY
Terminal Finish
TIN LEAD
Part Package Code
SOIC
Seated Height-Max
1.75 mm
Temperature Grade
INDUSTRIAL
Terminal Position
DUAL
Source Content uid
IDT74LVC112ADC
Number of Functions
2
Number of Terminals
16
Package Description
SOP, SOP16,.25
Prop. Delay@Nom-Sup
5.9 ns
Part Life Cycle Code
Obsolete
Qualification Status
Not Qualified
Load Capacitance (CL)
50 pF
Max Frequency@Nom-Sup
150000000 Hz
Package Body Material
PLASTIC/EPOXY
Reach Compliance Code
not_compliant
Propagation Delay (tpd)
7.1 ns
Package Equivalence Code
SOP16,.25
Operating Temperature-Max
85°C
Operating Temperature-Min
-40°C
Supply Voltage-Max (Vsup)
3.6 V
Supply Voltage-Min (Vsup)
2.7 V
Supply Voltage-Nom (Vsup)
3.3 V
Moisture Sensitivity Level
1
Peak Reflow Temperature (Cel)
240
Time@Peak Reflow Temperature-Max (s)
30
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