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2792 In Stock
IDT74LVC112APGG
2792 In Stock
IDT74LVC112APGG
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Manufacturer No:
Integrated Device Technology Inc
Manufacturer:
Integrated Device Technology Inc
Category:
FF/Latches
Package:
Datasheet:
Description Differential:
J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16
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Type
DESCRIPTION
Width
4.4 mm
Family
LVC/LCX/Z
Length
5 mm
HTS Code
8542.39.00.01
Objectid
2065433321
fmax-Min
150 MHz
Pin Count
16
Risk Rank
8.92
Rohs Code
Yes
Technology
CMOS
Pbfree Code
Yes
JESD-30 Code
R-PDSO-G16
Package Code
TSSOP
Trigger Type
NEGATIVE EDGE
JESD-609 Code
e3
Logic IC Type
J-K FLIP-FLOP
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Surface Mount
YES
Terminal Form
GULL WING
Number of Bits
2
Terminal Pitch
0.65 mm
Output Polarity
COMPLEMENTARY
Terminal Finish
MATTE TIN
Part Package Code
TSSOP
Seated Height-Max
1.2 mm
Temperature Grade
INDUSTRIAL
Terminal Position
DUAL
Source Content uid
IDT74LVC112APGG
Number of Functions
2
Number of Terminals
16
Package Description
TSSOP,
Part Life Cycle Code
Obsolete
Qualification Status
Not Qualified
Package Body Material
PLASTIC/EPOXY
Reach Compliance Code
compliant
Output Characteristics
3-STATE
Propagation Delay (tpd)
7.1 ns
Operating Temperature-Max
85°C
Operating Temperature-Min
-40°C
Supply Voltage-Max (Vsup)
3.6 V
Supply Voltage-Min (Vsup)
2.7 V
Supply Voltage-Nom (Vsup)
3.3 V
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