HTS Code

8542.39.00.01

Objectid

113758625

Max I(ol)

0.00061 A

Risk Rank

7.75

Rohs Code

Yes

Technology

CMOS

Subcategory

Gates

JESD-30 Code

R-PDIP-T14

Package Code

DIP

Logic IC Type

XOR GATE

Package Shape

RECTANGULAR

Package Style

IN-LINE

Surface Mount

NO

Terminal Form

THROUGH-HOLE

Packing Method

TUBE

Power Supplies

3/15 V

Terminal Pitch

2.54 mm

Schmitt Trigger

NO

Number of Inputs

2

Temperature Grade

INDUSTRIAL

Terminal Position

DUAL

Source Content uid

TC4030BP(F)

Number of Functions

4

Number of Terminals

14

Package Description

DIP, DIP14,.3

Prop. Delay@Nom-Sup

280 ns

Part Life Cycle Code

Active

Qualification Status

Not Qualified

Samacsys Description

Toshiba TC4030BP(F), Quad 2-Input XOR Logic Gate, 3 → 18 V, 14-Pin PDIP

Samacsys Modified On

2022-06-23 01:21:53

Load Capacitance (CL)

50 pF

Package Body Material

PLASTIC/EPOXY

Reach Compliance Code

unknown

Samacsys Manufacturer

Toshiba

Propagation Delay (tpd)

280 ns

Package Equivalence Code

DIP14,.3

Operating Temperature-Max

85°C

Operating Temperature-Min

-40°C

Supply Voltage-Max (Vsup)

18 V

Supply Voltage-Min (Vsup)

3 V

Supply Voltage-Nom (Vsup)

5 V