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2575 In Stock

SN74S114AN

2575 In Stock

SN74S114AN

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Manufacturer No:

Texas Instruments

Manufacturer:

Texas Instruments

Category:

FF/Latches

Package:

Datasheet:

Description Differential:

Dual J-K negative-edge-triggered flip-flops with preset, common CLR and CLK 14-PDIP 0 to 70

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    Type

    DESCRIPTION

    Width

    7.62 mm

    Family

    S

    Length

    19.305 mm

    HTS Code

    8542.39.00.01

    Objectid

    1438468728

    fmax-Min

    125 MHz

    Pin Count

    14

    Risk Rank

    9.37

    Rohs Code

    No

    Brand Name

    Texas Instruments

    Technology

    TTL

    Pbfree Code

    No

    Subcategory

    FF/Latches

    JESD-30 Code

    R-PDIP-T14

    Package Code

    DIP

    Trigger Type

    NEGATIVE EDGE

    Logic IC Type

    J-K FLIP-FLOP

    Package Shape

    RECTANGULAR

    Package Style

    IN-LINE

    Surface Mount

    NO

    Terminal Form

    THROUGH-HOLE

    Number of Bits

    2

    Power Supplies

    5 V

    Terminal Pitch

    2.54 mm

    Output Polarity

    COMPLEMENTARY

    Part Package Code

    DIP

    Seated Height-Max

    5.08 mm

    Temperature Grade

    COMMERCIAL

    Terminal Position

    DUAL

    Additional Feature

    WITH INDIVIDUAL SET INPUTS

    Source Content uid

    SN74S114AN

    Number of Functions

    1

    Number of Terminals

    14

    Package Description

    DIP, DIP14,.3

    Part Life Cycle Code

    Obsolete

    Qualification Status

    Not Qualified

    Package Body Material

    PLASTIC/EPOXY

    Reach Compliance Code

    not_compliant

    Propagation Delay (tpd)

    7 ns

    Package Equivalence Code

    DIP14,.3

    Operating Temperature-Max

    70°C

    Operating Temperature-Min

    Supply Voltage-Max (Vsup)

    5.25 V

    Supply Voltage-Min (Vsup)

    4.75 V

    Supply Voltage-Nom (Vsup)

    5 V

    Peak Reflow Temperature (Cel)

    NOTSPECIFIED

    Time@Peak Reflow Temperature-Max (s)

    NOTSPECIFIED

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